Analog Design Engineer, Senior Principal Pavia

Analog Design Engineer, Senior Principal
Pavia
Lombardia, Pavia

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

The Central Engineering – Optical PHY (CE-OPHY) team designs high-speed and optical transceivers for communication infrastructure in long-haul, metro, and datacenter. We address the bandwidth, capacity, and power issues faced by cloud computing and mega data centers that power social media giant platforms. Our innovative approaches have resulted in the company's products being first to market in many key areas, developing the most advanced chips and subsystems solutions to address the ever-increasing demand for higher data rates driven by video-on-demand, gaming, and other real-time data streams. We are seeking talented individuals to work on solving technical challenges with the most outstanding group of collaborators in the industry. Join our team of experts and make a difference in an exciting career opportunity. As a member of the dynamic CE-OPHY team, the candidate will be responsible for designing circuits used for high-speed optical transceivers. The member will have an opportunity to work in deep submicron processes and collaborate with the team on next-gen high-speed optical transceivers.

We are seeking for our Pavia, Italy site an experienced and versatile Analog Design Engineer to join our team. You will play a key role in developing multi-tens of GHz analog or DSP-based transceivers by designing analog circuits in advanced CMOS nodes (3nm and beyond).

What You Can Expect

Analyze block specifications and select appropriate topologies. Design analog blocks at the transistor level. Supervise layout activities, provide guidelines and conduct post-layout verifications. Model blocks and validate models. Collaborate with other teams to enhance existing solutions. Take responsibility for designing entire analog macros or IPs. Participate in cross-functional meetings and interact with other functions. Manage both pre-silicon and post-silicon tasks through to mass production. Train and mentor junior designers. What We're Looking For

Master's degree and/or PhD in Electrical Engineering or related fields with 12-15 years of work experience. Proven experience in designing ICs from architecture definition to lab characterization and bringing them into volume production. Solid experience in analog design, preferably in the multi-GHz range; performing or supervising analog custom layout; using EDA CAD tools; measuring IC performance and debugging the design to correlate simulations to measurements. Direct project experience in at least one of the following areas a plus: Multi-Gbps electrical SerDes or electro-optical transceivers; advanced CMOS nodes, including FinFET. Strong communication, presentation, and documentation skills. Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We're dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it's like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability, or protected veteran status.

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