Asic Digital Design - Serdes | Master Thesis Internship
At Synopsys, we're at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we're powering it all with the world's most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you. Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world's broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities, meet unique performance, power, and size requirements of their target applications, and get differentiated products to market quickly with reduced risk. ASIC Digital Design Intern We are seeking a highly motivated and innovative MS student in microelectronics engineering with an interest in ASIC development flow. The candidate will work as part of a highly experienced mixed-signal design and verification team, targeting the current and next generation PAM-based SerDes products. Some theoretical background in high-speed serializer and data recovery circuits is a strong plus. This position offers an excellent opportunity to work with an expert team of digital and mixed-signal engineers responsible for delivering high-end mixed-signal designs from specification development to performing functional and performance tests on prototype test-chips. The PHY IP development is dynamic and provides an endless list of challenges. The candidate will receive initial training from top experts in the field as well as continuous on-the-job training and assignments. The work is challenging, given the constant technological changes and the ownership required to navigate unknown waters. Key Qualifications MSEE student with almost all exams completed Good theoretical understanding of digital signal processing Good communication skills for interacting between different design groups and customer support teams Must be self-motivated, proactive, and able to balance good design quality while meeting tight deadlines Ability to resolve issues creatively and exercise independent judgment in selecting methods and techniques to obtain solutions Preferred Experience Familiarity with Verilog and VCS, knowledge of back-end synthesis tools DC / PT Some knowledge of digital design methodologies, ATE production testing, DFT insertion, synthesis constraints, and flows Scripting experience in Shell, Perl, Python, and TCL is a plus Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability. Synopsys Italy values the diversity of our workforce. We are committed to providing access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact [emailprotected]. J-18808-Ljbffr
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