Asic Digital Design, Sr Engineer Bardi

Asic Digital Design, Sr Engineer
Bardi
Emilia Romagna, Bardi

Seeking a highly motivated and innovative design engineer with background in high-speed protocols. Working as part of an experienced digital design and verification team. The position offers an excellent opportunity to work with experts on several fields. The candidate will be involved at specify, design and implement phases of state-of-the-art products. Key responsibilities: Study standard specifications published by JEDEC Define micro architecture at block level based on IP architecture Work on RTL design based on predefined coding style, SVA is included Clean RTL check violations in lint, CDC, DFT and synthesis Run block level test to speed up IP verification Work with verification to debug and fix RTL issues Check synthesis timing and improve RTL design if required Required Skills: 1-year of relevant IP design experience Desire to learn and explore new technologies Demonstrate good investigation and problem-solving skills Be familiar with IP design flow and good at RTL design Solid RTL debug capability Knowledge in HBM/DDR and interface technologies such as UCie, PCIe, USB is a plus Knowledge in FrontEnd and/or BackEnd synthesis is a plus J-18808-Ljbffr