Asic Mixed-Signal (Analog/Digital) Verification Engineer Bardi

Asic Mixed-Signal (Analog/Digital) Verification Engineer
Bardi
Emilia Romagna, Bardi

Synopsys, a world leader in the Semiconductor IP industry, is seeking a Mixed Signal Verification Engineer whose responsibilities are:

Main Responsibilities: Work in a Digital and Verification Development team contributing to the development and validation of complex digital mixed signals for high-speed interface IP, having major focus on Analog SchematicsDebug and verify the Analog schematics, support to Analog teams, to faster verify the functionality of Analog SchematicsUnderstand the IP from a System level, Analog and Digital interactionsEngage in verification activities of analog Designs, under supervision of more experienced personnel, and to exercise judgment to determine appropriate actions to achieve the required specifications. Be able to debug and understand issues related with malfunctions on analog designsExposure to mixed signal validations flow. Co-sim. Build productive working relationships, with different teams, cross projectParticipate in applicable product/project reviews. Prepare and present reports outlining the outcome of technical projects. Preferred Technical Experience: Experience in producing high-quality technical documentation is desirableExperience with analog tools, preferable Synopsys toolsGood understanding of analog designExperience in Verilog/VHDLProficiency in at least one programming language such as Python, C, C++ and MATLABExperience in System Verilog /VMM/UVMExposure to Unix, Perl and TCL scriptingOther Qualifications: University master's degree in electronic/Micro-electronics engineering5+ years of relevant experience is highly preferredKnowledge of IC design flowsAnalog design knowledge, Digital design understandingAnalog tools and spice simulators understandingDigital verification tools understandingWillingness to learn new things. Good team-player with organizational and problem-solving skillsGood English communication skills

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