Asic Mixed-Signal (Analog/Digital) Verification Engineer
Synopsys, a world leader in the Semiconductor IP industry, is seeking a Mixed Signal Verification Engineer whose responsibilities are:
Main Responsibilities: Work in a Digital and Verification Development team contributing to the development and validation of complex digital mixed signals for high-speed interface IP, having major focus on Analog Schematics.
Debug and verify the Analog schematics, support to Analog teams, to faster verify the functionality of Analog Schematics.
Understand the IP from a System level, Analog and Digital interactions.
Engage in verification activities of analog Designs, under supervision of more experienced personnel, and to exercise judgment to determine appropriate actions to achieve the required specifications.
Be able to debug and understand issues related with malfunctions on analog designs.
Exposure to mixed signal validations flow.
Co-sim.
Build productive working relationships, with different teams, cross project.
Participate in applicable product/project reviews.
Prepare and present reports outlining the outcome of technical projects.
Preferred Technical Experience: Experience in producing high-quality technical documentation is desirable.
Experience with analog tools, preferable Synopsys tools.
Good understanding of analog design.
Experience in Verilog/VHDL.
Proficiency in at least one programming language such as Python, C, C++ and MATLAB.
Experience in System Verilog / VMM / UVM.
Exposure to Unix, Perl and TCL scripting.
Other Qualifications: University master's degree in electronic/Micro-electronics engineering.
5+ years of relevant experience is highly preferred.
Knowledge of IC design flows.
Analog design knowledge, Digital design understanding.
Analog tools and spice simulators understanding.
Digital verification tools understanding.
Willingness to learn new things.
Good team-player with organizational and problem-solving skills.
Good English communication skills.
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