Digital Ic Verification Engineer Parma

Digital Ic Verification Engineer
Parma
Emilia Romagna, Parma

Working for a leader in power electronics, this is a great opportunity to join a growing team as a UVM Verification Engineer.

Job Duties: Developing test plans, tests, and verification infrastructure using SV/UVM methodologyBuilding reusable bus functional models, monitors, checkers, and scoreboardsPerforming coverage-driven verification closurePerforming block-level, multi-block level, and system-level verificationPerforming gate-level simulationsPerforming mixed-signal simulationsImplementing regression testsPerforming formal verificationWorking closely with IC designers and post-silicon engineersQualifications and Background: Requirements:Knowledge/experience with HDL (SystemVerilog / Verilog / VHDL), particularly for testbench creationKnowledge/experience in scripting languages, such as Tcl and PythonSome knowledge of ASIC design flow and related verification stepsNice to have:Some experience in digital RTL designKnowledge of UVM environments and classesSome experience with main EDA vendor simulators such as Questasim and XceliumKnowledge of DFT structures and test pattern generationSome experience in silicon validation/characterizationExperience working on Git. For more information, please contact Rob Hudson. Please note that if you are NOT a passport holder of the country for the vacancy, you might need a work permit. Bank or payment details should not be provided when applying for a job.

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