Digital Verification Engineer
OUR STORY At ST, we believe in the power of technology to drive innovation and make a positive impact on people, business, and society.
We are a global semiconductor company, and our advanced technology chips forms the hidden part of the world we live in today.
When you join ST, you will be part of a global business of more than 115+ nationalities and present in 40 countries, 50, 000+, diverse and dedicated creators makers of technology around the world!
Developing technologies takes more than talent: it takes amazing people who understand collaboration and respect.
People with passion and desire to disrupt the status quo, push boundaries and drive innovation – whilst unlocking your own potential.
Working at ST means innovating for a future that we want to make smarter, greener, in a responsible and sustainable way.
Our technology starts with you.
Join us and start the future!
YOUR ROLE The position is aimed at a digital verification engineer preferably with previous experience in digital verification of ASIC (principal features are DSP and advanced digital control logics).
The preferred seniority is 3 to 5 years of experience.
The candidate will be placed in the digital verification team of MEMS Sub-Group and will have the possibility to follow all the ASIC verification process from specification definition up to final product industrialization.
He/She is able to implement a verification environment model of DSP and digital control logic starting from ASIC specification and to write tests.
He/She follows the ASIC verification from specification definition up to silicon release.
The level of autonomy and responsibility will be evaluated during the selection process.
He/She will interact directly with other verification engineers and the design team during the development phase and may be directly involved in silicon debug.
YOUR SKILLS EXPERIENCES Master's degree in electronic engineering or similar 3-5 years of experience in a similar role Background in Digital verification Testbenches (VHDL or Verilog) System Verilog knowledge Experience with digital simulator tools (Universal Verification Methodology knowledge is preferred) Basic knowledge of MATLAB toolboxes or similar tools System Verilog Assertion, python scripts, tcl scripts and formal verification are considered a plus We encourage candidates who may not meet every single requirement to apply, as we appreciate diverse perspectives and provide opportunities for growth and learning.
Diversity, Equity and Inclusion (DEI) is part of our company culture.
Our DEI vision is, "At ST, you can be the true version of yourself", we value all employee contributions and have zero tolerance for any kind of discrimination.
Joining us is also about a greater work-life balance and a workplace with equal opportunities.
Dedicated Employee Resource Groups for women and LGBTQIA+, hybrid work arrangements are amongst the many DEI Sustainability initiatives that make us a great place to evolve your career.
To discover more, visit st.com/careers #J-18808-Ljbffr
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