Junior Asic Design Engineer Lazio

Junior Asic Design Engineer
Roma
Lazio, Lazio

ASIC Design Engineer Remote anywhere in Italy My Client is looking for an ASIC / Logical Design Engineer to join their hardware design team.

In this role, you will contribute to developing cutting-edge AI-driven silicon solutions while working with a talented team of engineers to optimize performance, power, and area (PPA).

Key Responsibilities Collaborate with cross-functional teams to define and refine design specifications.

Use industry-standard tools to design and optimize digital logic circuits.

Conduct block and system-level RTL coding, focusing on PPA metrics.

Integrate IPs/Sub IPs into the top-level SoC.

Perform static checks (lint, CDC, equivalence) and automate tasks for efficiency.

Collaborate with verification engineers to ensure design correctness and functional verification.

Work with physical design engineers on DFM/DFT considerations.

Experience required Advanced degree in Electrical Engineering, Computer Engineering, or related field.

Experience with SystemVerilog, synthesis, timing analysis, and DFT.

Proficiency in scripting (Python, TCL) for automation and advanced tool scripting.

Strong analytical, problem-solving, and debugging skills.

Excellent communication and ability to work in a remote, diverse team.

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